Electrical engineering · Avionics hardware

CharlesBecker

I design circuits that have to survive things that would kill a normal board, from lightning strikes and EMI to surges and power-line faults. The protection, filtering and power integrity go in from the first schematic, not after a failed test.

B.S. Electrical Engineering · Minor in Aerospace · University of Arizona Electrical Engineering Co-op · Parker Aerospace

EMI filter design
Transient & surge protection
Altium schematic & PCB layout
LTspice simulation
DO-160G & DO-254 hardware

See the boards Get in touch

Working on now: The Brain

Flight hardware

Parker Aerospace

I've worked on three boards for Parker's 3rd-generation aircraft camera line, which expands visibility around the aircraft during ground maneuvers. The PIB and fault monitor designs belong to Parker, so those two stick to what's public. In person, I'm glad to talk through my general design process and the skills behind them.

Done In progress Up next Not applicable

Render of Parker's 3rd-generation aircraft camera, the unit the PIB goes into

Charles holding the 3rd-generation camera at a Parker Technology Day

ProprietarySchematic and layout stay with Parker. In person, I can walk through my design process and the skills behind it.

PCB · Parker Aerospace In test & certification

PIB

Protection & Interface Board

The board between the aircraft and the camera. Power, discrete I/O and Gigabit Ethernet all pass through it on the way in. I took it from a blank Altium sheet through component selection, simulation, an 8-layer layout, documentation and design review.

Role: Hardware design
Dates: May – Aug 2026
Tools: Altium · LTspice
Next: Test & certification

Design flow

Arch
Sch
Sim
Layout
Review
Test
Cert

Lightning transientsDO-160G §22 · Cat A4G4 · Level 4

Custom protection on high-speed, low-speed, power and discrete lines, simulated in LTspice.

Power input & spikes§16 Cat B · §17 Cat A

Dedicated protection circuitry on the 28 V power lines.

RF susceptibility & emissions§20 Cat TT · §21 Cat H

Multistage CM/DM π-filter tuned to the main regulator's switching frequency, designed with DC-bias derating, SRF, ESR, ESL and harmonics accounted for.

Gigabit EthernetIEEE 802.3ab · 1000BASE-T

Full Gigabit Ethernet implementation, carrying 4K video at 60 fps.

Board stackup8-layer PCB

Laid out as an 8-layer board in Altium, fitting the lightning protection, EMI filtering and Gigabit Ethernet routing into one compact PCBA.

Power redundancy2 × 28 V DC · active diode-OR

Keeps the camera powered without interruption if either rail drops out.

3D render of the top of the PIT: FPC connectors, test points and the board-to-board connectors

PIT PCB layout showing the differential pair routing

PCB · Parker Aerospace In test

PIT

Test board · PIB and camera sensor board

A test board that wires the 3rd-gen camera's E1 sensor board and PIB into our white-label prototype setup. It mounts on the earlier-design FPGA card, which fits every revision of the chassis, so both boards can go through bring-up and environmental testing before the full camera exists. I took it through schematic capture and layout in Altium, and it's now midway through test.

Signal path on the bench

Sensor boardMIPIPrototype setup1000BASE-TPIB1 GbE out

Role: Schematic & layout
Dates: Oct 2026
Tools: Altium
Setup: White-label

Design flow

Arch
Sch
Sim
Layout
Review
Test
Cert

Parallel validationEarlier FPGA card · every chassis revision

Because the PIT fits the earlier-design FPGA card, the sensor board and PIB can go through vibration, thermal and other environmental testing now, in parallel with the FPGA, processor and fault monitoring boards that are still being designed.

MIPI from the E1 sensor boardFPC to FPC · 85 Ω differential

The sensor board's MIPI lanes cross the PIT between two fine-pitch FPC connectors and land on the prototype setup, so it gets the same image data it will get inside the camera.

PCIe and EthernetPCIe · 1000BASE-T

PCIe lanes are routed as 85 Ω differential pairs, and the 1000BASE-T path runs across the PIT to the PIB, so the PIB's Ethernet path, protection included, carries the camera's video on the bench.

Differential pair routing85 Ω · length-matched · from the stackup

Every MIPI and PCIe pair is routed at 85 Ω differential and length-matched within the pair. I set trace width and spacing from the board stackup so the impedance holds layer to layer.

Crosstalk controlPerpendicular crossovers

Wherever signals cross on adjacent layers they cross at 90°, which keeps parallel coupling, and the crosstalk that comes with it, off the high-speed pairs.

Altium layoutPolygon planes · stackup · high-speed vias

Polygon pours for the power and ground planes, impedance-controlled geometry worked out from the stackup, and high-speed vias checked with the Saturn PCB Design Toolkit.

Probe access20 test points · power input

Color-coded test points on power, ground and key signals, plus a dedicated power connector, for bring-up and debug.

Independent project · Open source

PCB · Independent Finishing schematics

The Brain V1

Flight computer, sensor hub and telemetry transceiver on one board

University design-build-compete teams spend months building avionics from scratch, or they all fly the same third-party flight computers. Those boards work well, but they're often overkill and expensive, they can't be built or repaired in house, and when every team runs the same hardware, nothing sets yours apart in systems papers or award judging.

I talked with UArizona teams to pin down what they actually need, so The Brain covers those requirements without becoming another overkill board: a flight computer, a sensor hub and a redundant telemetry link on one board, built around the RP2350B. Teams start from a strong baseline they can build, modify and explain themselves, so they get flying sooner and spend their time iterating on their own systems. It will be released open source with full documentation.

Role: Designer
Dates: Jul 2026 – present
Tools: Altium · LTspice
Firmware: C++ · RadioLib

Design flow

Arch
Sch
Sim
Layout
Review
Test
Cert

Built for UArizona competition teams like IREC and NASA Lunabotics.

The Brain V1 system architecture: RP2350B microcontroller with QSPI program flash and a data-log flash; main and redundant SX1280 radios with front-end modules feeding an SPDT RF switch, 2.4 GHz band-pass filter, ESD protection and antenna; two barometers and magnetometers on separate I2C buses; two precision and two high-g IMUs on SPI; CAN FD controller and transceiver; 9 to 36 V to 5 V to 3.3 V power with EMI filters, a diode-OR with USB-C 5 V, with per-rail latch-up protection marked TBD; protection on every line of the Harwin Datamate J-Tek connector.

StatusSchematic capture → LTspice

Finishing schematic capture and starting simulation in LTspice.

TelemetryRedundant 2.4 GHz

A redundant telemetry chain designed in Altium: dual SX1280 transceivers with FEMs on independent SPI buses, one SPDT RF switch, a π band-pass filter and ESD protection.

Power9–36 V input

Surge and transient protection and EMI filtering ahead of switching regulators to 5 V (400 kHz) and 3.3 V (2.4 MHz).

Vehicle busCAN FD over SPI

The RP2350B flight computer has no native CAN, so a CAN FD controller pairs with a CAN FD transceiver over an SPI interface.

Proof of concept915 MHz LoRa · 5 mi

ESP32-S3 and SX1262 dev boards running C++ RadioLib firmware with channel activity detection. Tested at 5 miles line of sight, 5 nodes to 1 gateway.

Parker Aerospace · In progress

PCB · Parker Aerospace In progress

Fault Monitor

Plug-in board for the camera's DAL C option

The 3rd-gen camera will offer a DAL C option, added through a small plug-in board I'm designing. Its ADC-based detection checks the camera's inputs and outputs, knows when each function should be on (including when the heaters should run), and raises an alert when the camera isn't working correctly. The architecture is proprietary and patent pending, so this is the high-level version.

Role: Designer
Dates: Aug 2026 – present
Tools: Altium · LTspice
IP: Patent pending

Design flow

Arch
Sch
Sim
Layout
Review
Test
Cert

Reliability targetDAL C · DO-254

Monitoring that lets the camera line meet Design Assurance Level C.

Coverage> 1 × 10⁻⁵ per flight hour

Every camera area above this failure probability gets detection.

Form factorSmall plug-in board

Adds the DAL C option to the 3rd-gen camera as a plug-in board.

DetectionADC-based monitoring

Checks inputs and outputs against the rules for when each part of the camera should be on, including heater operation, and flags the camera as not functioning correctly when they don't match.

My partFailure analysis → schematic → layout

Mapping where the camera can fail, then capturing the monitoring circuits, simulating them in LTspice and taking them to layout in Altium.

PatentPending

Contributing design work to a fault-detection architecture that reaches DAL C without requiring sub-threshold component failure rates.

Community

SHPE

Society of Hispanic Professional Engineers, University of Arizona chapter. SHPE is where I give back: raising money so more students can reach the national convention, building tools that help engineering students prepare, and showing high school students what an engineering path can look like.

Apr 2025 – May 2026

Executive board · Academic Coordinator

Elected by the chapter. Built out the chapter's practice test bank and internship bank, and organized study sessions for engineering students.

Every year

~$5,000 raised for convention scholarships

Led campus fundraising that sends students to the SHPE National Convention.

Mar 2025

Panelist · Advancement of Latinx in Engineering

Shared my journey in engineering and entrepreneurship, then volunteered at hands-on workshops with Arizona high school students.

Oct 2024 – present

Member

Community outreach and professional development across SHPE Region 2.

Charles, newly elected Academic Coordinator, with the outgoing Academic Coordinator at the SHPE UA banquet

Charles speaking on the Advancement of Latinx in Engineering panel

The panel on stage beneath the slide introducing each panelist

Charles with fellow SHPE members at the 2025 National Convention

Group photo behind the FAMILIA sign at the SHPE 2025 National Convention

Also at the University of Arizona

Ribbon cutting at the Nano Fabrication Center's semiconductor cleanroom

Charles and a colleague with a cart of XR headsets

Ribbon cutting posters describing the XR classroom and immersive learning

Jun 2025 – present

Engineering technician · UA College of Engineering

I support the college's research groups, coordinating with faculty and vendors to resolve issues quickly.

That work included helping set up and unveil the Nano Fabrication Center's semiconductor cleanroom and its Extended Reality classroom, where students train on digital twins of the cleanroom tools before they ever step inside.

18 XR learning stations
Apple Vision Pro · Meta Quest 3
Digital twins
Opened Feb 2026

Jul 2025 – May 2026

Co-founder · UA NASA Lunabotics

Co-founded the team under STAR-X, helped raise $7,500 from the university and grew it past 15 active members.

Toolbelt

What I work with

Domain

Transient & surge protection
EMI filter design (CM/DM)
Conducted & radiated emissions
Component derating
Power redundancy

Design & simulation

Altium Designer
LTspice · PSpice
KiCad · OrCAD
SolidWorks
MATLAB · C/C++

Standards

DO-160G §16 17 20 21 22 25
DO-254
IEEE 802.3ab

Interfaces

1000BASE-T · PCIe · MIPI
CAN FD · RS-485
I²C · SPI · UART · USB

Bench

Oscilloscope · DMM
Power supply · signal generator
SMD & THT soldering
Spot welding · 3D printing

Contact

Let's talk hardware.

Find me at a conference, or reach out anytime about internships, co-ops or the boards on this page.

charlesnbecker@arizona.edu

LinkedIn ↗

Tucson, AZ
U.S. Citizen
B.S. EE · expected Dec 2028

Charles in a Tony Stark Halloween outfit with a glowing chest piece and a light-up gauntlet — Off the clock: a Tony Stark fit I made for Halloween, lit by a battery pack I built with my spot welder and 3D printer.